Current-aware floorplanning to overcome current delivery limitations in integrated circuits
US8863068B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 18, 2012 |
| Grant date | Oct 14, 2014 |
| Priority date | — |
| Expiry date | Oct 11, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dynamic system coupled with “pre-Silicon” design methodologies and “post-Silicon” current optimizing programming methodologies to improve and optimize current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The mechanism consists of measuring or estimating power consumption at a certain granularity within a chip, converting the power information into C4 current information using a method, and triggering throttling mechanisms (including token based throttling) where applicable to limit the current delivery per C4 beyond pre-established limits or periods. Design aids are used to allocate C4s throughout the chip based on the current delivery requirements. The system coupled with design and programming methodologies improve and optimize current delivery is extendable to connections across layers in a multilayer 3D chip stack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.