Packaging system for protection of IC wafers during fabrication, transport and storage
US8863956B2 · kind B2 · utility
Inventors
Key dates
| Filing date | Jan 17, 2012 |
| Grant date | Oct 21, 2014 |
| Priority date | — |
| Expiry date | Dec 29, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/67396
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The packaging system includes an enclosure having an interior volume. A wafer stack, comprising plural wafers and separators in contact with the wafers, is located in the interior volume. The separators have raised bumps extending from each side. The bumps create spaces that allow air to flow therethrough. The separator film intercepts and captures airborne molecular contaminants belonging to organic and inorganic chemical families. In addition, the film is dissipative to static discharge. Furthermore, the bumps provided by the separators protect the fragile wafers from damage due to mechanical shock. The separators are also provided with a peripheral ring or embossment, which contacts the wafer edges and further protects the wafers from damage to mechanical shock. Air cushions can be provided in the wafer stack, which cushions are provided with bands to regulate the compression.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.