Memory device and method for manufacturing same
US8866119B2 · kind B2 · utility
1Cited by
0References
7Claims
0Family size
Assignee
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Key dates
| Filing date | Mar 18, 2011 |
| Grant date | Oct 21, 2014 |
| Priority date | — |
| Expiry date | Jun 22, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/72
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, a memory device includes a selection element layer, a nanomaterial aggregate layer, and a fine particle. The nanomaterial aggregate layer is stacked on the selection element layer. The nanomaterial aggregate layer has a plurality of micro conductive bodies aggregated with an interposed gap. The fine particle has at least a surface made of silicon oxynitride. The fine particle is dispersed between the micro conductive bodies in one portion of the nanomaterial aggregate layer piercing the nanomaterial aggregate layer in a thickness direction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.