Non-volatile memory device and production method thereof

US8866123B2 · kind B2 · utility

Assignee

• HITACHI, LTD. · JP

Inventors

• Yoshitaka Sasago · Tachikawa, JP
• Masaharu Kinoshita · Tokyo, JP
• Takahiro Morikawa · Tokyo, JP
• Akio Shima · Hino, JP
• Takashi Kobayashi · Suzaka, JP

Key dates

• Filing date: Nov 22, 2010
• Grant date: Oct 21, 2014
• Expiry date: Nov 22, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10N70/8265

Abstract

A vertical chain memory includes two-layer select transistors having first select transistors which are vertical transistors arranged in a matrix, and second select transistors which are vertical transistors formed on the respective first select transistors, and a plurality of memory cells connected in series on the two-layer select transistors. With this configuration, the adjacent select transistors are prevented from being selected by respective shared gates, the plurality of two-layer select transistors can be selected, independently, and a storage capacity of a non-volatile storage device is prevented from being reduced.