Optoelectronic semiconductor chip
US8866175B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 22, 2011 |
| Grant date | Oct 21, 2014 |
| Priority date | — |
| Expiry date | Aug 22, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10H20/84
Abstract
An optoelectronic semiconductor chip includes a semiconductor layer sequence and a carrier substrate. A first and a second electrical contact layer are arranged at least in regions between the carrier substrate and the semiconductor layer sequence and are electrically insulated from one another by an electrically insulating layer. A mirror layer is arranged between the semiconductor layer sequence and the carrier substrate. The mirror layer adjoins partial regions of the first electrical contact layer and partial regions of the electrically insulating layer. The partial regions of the electrically insulating layer which adjoin the mirror layer are covered by the second electrical contact layer in such a way that at no point do they adjoin a surrounding medium of the optoelectronic semiconductor chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.