Vertical gate LDMOS device
US8866217B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 10, 2012 |
| Grant date | Oct 21, 2014 |
| Priority date | — |
| Expiry date | Aug 10, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/663
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Described here are transistors and fabrication methods thereof. In one implementation, a transistor includes an n-well region implanted into a surface of a substrate, and a trench in the n-well region. The trench extends from the surface to a first depth. The trench includes a gate of conductive material in the trench, and dielectric material filling a volume of the trench not filled by the conductive material. The transistor also includes a p-type material in a first region extending from a second depth to a third depth, the second depth and the third depth being greater than the first depth. The transistor further includes a source region and a drain region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.