Semiconductor device with vertical channel transistor and method of operating the same
US8866219B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 2, 2011 |
| Grant date | Oct 21, 2014 |
| Priority date | — |
| Expiry date | May 9, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/513
Abstract
Provided is a semiconductor device including a substrate having active patterns extending between first trenches and between second trenches (the first and second trenches intersecting each other), and gate patterns disposed within the first trenches, wherein each of the active patterns includes lower and upper impurity regions, and a channel region between the lower and upper impurity regions, the lower and upper impurity regions being vertically spaced apart from each other and having a conductivity type different from the substrate, and the channel region having the same conductivity type as the substrate, and a bottom surface of the gate pattern is closer to a bottom surface of the first trench than the lower impurity region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.