Display device
US8866224B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 5, 2013 |
| Grant date | Oct 21, 2014 |
| Priority date | — |
| Expiry date | Apr 27, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/60
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
Disclosed are a TFT array substrate for decreasing a bezel width and a display device including the same. The display device includes a first substrate including a display area (including a pixel formed in a pixel area defined by a gate line and a data line which intersect) and a non-display area that includes a built-in shift register connected to the gate line and a gate link part connected to the built-in shift register, a second substrate facing the first substrate, and a seal pattern formed in the non-display area of the first substrate in correspondence with an edge portion of the second substrate to facing-couple the first and second substrates. The seal pattern includes a first hardening area hardened by a first hardening process, and a second hardening area hardened by a second hardening process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.