Chip package structure and method of making the same
US8866283B2 · kind B2 · utility
19Cited by
23References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 17, 2012 |
| Grant date | Oct 21, 2014 |
| Priority date | — |
| Expiry date | Apr 5, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/5313
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods and structures related to packaging a chip are disclosed. In one embodiment, a chip package structure includes: (i) a chip having a plurality of first and second contact pads thereon; (ii) a lead frame having a plurality of pins for external connection to the package structure, where the chip is disposed on the lead frame; (iii) a plurality of first bonding wires for connecting the first contact pads to the lead frame; and (iv) a plurality of second bonding wires for connecting the second contact pads to the plurality of pins on the lead frame.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.