Chip package structure
US8866309B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 27, 2012 |
| Grant date | Oct 21, 2014 |
| Priority date | — |
| Expiry date | Apr 22, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15786
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A first back surface of a first chip faces toward a carrier. A first active surface of the first chip has first pads and a first insulting layer thereon. A second chip is disposed on the first chip and electrically connected to the carrier. A second active surface of the second chip faces toward the first active surface. The second active surface has second pads and a second insulting layer thereon. Bumps connect the first and second pads. First and second daisy chain circuits are respectively disposed on the first and second insulting layers. Hetero thermoelectric device pairs are disposed between the first and second chips and connected in series by the first and second daisy chain circuits, and constitute a circuit with an external device. First and second heat sinks are respectively disposed on a second surface of the carrier and a second back surface of the second chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.