Digital delay-locked loop circuit using phase-inversion algorithm and method for controlling the same
US8866522B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 21, 2014 |
| Grant date | Oct 21, 2014 |
| Priority date | — |
| Expiry date | May 21, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0818
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Disclosed herein are a delay-locked loop circuit using a phase inversion locking algorithm and a method of controlling the same. There is provided a delay-locked loop circuit using a phase inversion locking algorithm, including a phase inversion controller configured to control whether or not to use the phase inversion locking algorithm by determining a phase error between an input clock signal and an output clock signal, an inverter configured to invert the input clock signal and output the inverted input clock signal, a multiplexer configured to receive the input clock signal and the inverted input clock signal of the inverter and output the input clock signal in response to the control signal of the phase inversion controller or the inverted input clock signal, and a delay-locked loop connected to the output terminal of the multiplexer and configured to perform phase synchronization in response to the output signal of the multiplexer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.