Dual flip-flop circuit
US8866528B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 2, 2012 |
| Grant date | Oct 21, 2014 |
| Priority date | — |
| Expiry date | Jan 6, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356121
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A dual flip-flop circuit combines two or more flip-flip sub-circuits into a single circuit. The flip-flop circuit comprises a first flip-flop sub-circuit and a second flip-flop sub-circuit. The first flip-flop sub-circuit comprises a first storage sub-circuit configured to store a first selected input signal and transfer the first selected input signal to a first output signal when a buffered clock signal transitions between two different logic levels and a dock driver configured to receive a clock input signal, generate an inverted clock signal, and generate the buffered clock signal. The second flip-flop sub-circuit is coupled to the clock driver and configured to receive the inverted clock signal and the buffered clock signal. The second flip-flop sub-circuit comprises a second storage sub-circuit configured to store a second selected input signal and transfer the second selected input signal to a second output signal when the buffered clock signal transitions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.