Apparatus and method for reducing sampling circuit timing mismatch
US8866652B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 24, 2013 |
| Grant date | Oct 21, 2014 |
| Priority date | — |
| Expiry date | Aug 24, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/1215
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An example apparatus, system, and method for sampling in an interleaved sampling circuit having multiple channels. In an embodiment, an input clock is used to synchronize the transitions of sampling clocks from a first to second voltage level, relative to one another. The sampling clocks are input to a sampling circuit. The input clock switches a common switch that pulls each sampling clock to the second voltage level through a common path on input clock transitions from a first to a second clock state. The transition from the first to a second voltage level of each sampling clock triggers a sample taken on one of the channels. The first voltage level may be boosted to drive switches on in the sampling circuit. Synchronizing transitions of the outputs through the common switch and common path reduces timing mismatch between the sampling clocks controlling the channels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.