Node level vectoring synchronization
US8867404B2 · kind B2 · utility
1Cited by
0References
18Claims
0Family size
Assignee
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Key dates
| Filing date | Feb 3, 2012 |
| Grant date | Oct 21, 2014 |
| Priority date | — |
| Expiry date | Oct 29, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/2692
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An apparatus for synchronizing a plurality of digital subscriber line access multiplexers (DSLAMs) comprising a reference clock configured to generate a reference clock signal, and an interface configured to transmit the reference clock signal to the DSLAMs, wherein each of the DSLAMs is configured to align its system clock with the reference clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.