Low latency synchronizer circuit
US8867684B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 5, 2013 |
| Grant date | Oct 21, 2014 |
| Priority date | — |
| Expiry date | Sep 5, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/0375
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An apparatus for synchronizing an incoming signal with a clock signal comprises two or more synchronizer circuits, wherein each synchronizer circuit receives the incoming signal and the clock signal. Each synchronizer circuit generates a synchronized signal, wherein the state of each synchronized signal changes on a different phase of said clock signal in response to a change of the state of said incoming signal. A decision mechanism circuit receives the synchronized signals generated by each synchronizer circuit, wherein the decision mechanism circuit determines the output signal in response to the change of the state of the incoming signal. The decision mechanism circuit further comprises a memory element having a state which is set according to a previously detected state of said signal, wherein the output signal is determined according to the state of the memory element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.