Processor and cache arrangement with selective caching between first-level and second-level caches
US8868833B1 · kind B1 · utility
2Cited by
11References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 2, 2011 |
| Grant date | Oct 21, 2014 |
| Priority date | — |
| Expiry date | Oct 6, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/084
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Approaches for caching addressable items in a multiprocessor system. Instructions are cached in a plurality of first-level instruction caches respectively coupled to a plurality of processors of the multiprocessor system. First-type data items are cached in a plurality of first-level data caches respectively coupled to the plurality of processors. Second-type data items are cached in a second-level cache and are not cached in any of the plurality of first-level data caches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.