Patent · US Active

Synchronous clock stop in a multi nodal computer system

US8868960B2 · kind B2 · utility

3Cited by

2References

12Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Tobias U. Bergmann · Eppelheim, DE
Ralf Ludewig · Schenefeld, DE
Tobias Webel · Eppelheim, DE
Ulrich Weiss · Holzgerlingen, DE

Key dates

Filing date	Jun 28, 2011
Grant date	Oct 21, 2014
Priority date	—
Expiry date	Apr 11, 2033

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02D10/00
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A computer system is provided which includes a plurality of nodes, which include chips of different types. In each node, one of the chips is configured as a master chip, which is connected to one or more slave chips via two or more multi-drop nets (e.g., checkstop, clockrun). The master chip and the slave chips are connected to a reference clock, and event triggering information is transmitted via the multi-drop nets (checkstop, clockrun) to the slave chips. Event trigger commands are submitted by the master chip when it receives a request, and internal offset counters are used to adjust both the receiving cycle and the cycle when the command is propagated to the units on the chips. In operation, the offset counters are synchronized by a reference clock.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.