Partial fault processing method in computer system
US8868968B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 23, 2012 |
| Grant date | Oct 21, 2014 |
| Priority date | — |
| Expiry date | Nov 15, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2038
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
As regards a hardware fault which has occurred in a computer, a hypervisor notifies an LPAR which can continue execution, of a fault occurrence as a hardware fault for which execution can be continued. Upon receiving the notice, the LPAR notifies the hypervisor that it has executed processing to cope with a fault. The hypervisor provides an interface for acquiring a situation of a notice situation. It is made possible to register and acquire a situation of coping with a hardware fault allowing continuation of execution through the interface, and it is made possible to make a decision as to the situation of coping with a fault in the computers as a whole.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.