System-level testcase generation
US8868976B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 4, 2010 |
| Grant date | Oct 21, 2014 |
| Priority date | — |
| Expiry date | Sep 10, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3684
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system-level testcase may be generated by performing system-level generation tasks by a system-level generator to produce an abstract testcase. Based upon the abstract testcase, one or more unit-level generators may generate the testcase. The testcase may be utilized in simulation of operation of a system-under-test (SUT). The testcase may be utilized for verification of the SUT. The SUT may comprise a plurality of units. The unit-level generator may be associated with units of the SUT and perform generation tasks associated with pertinent units.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.