Stretch dummy cell insertion in FinFET process
US8869090B2 · kind B2 · utility
5Cited by
0References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 15, 2013 |
| Grant date | Oct 21, 2014 |
| Priority date | — |
| Expiry date | Mar 15, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method embodiment includes identifying an empty region in an integrated circuit (IC) layout, wherein the empty region is a region not including any active fins and outside a minimum spacing boundary, applying a grid map over the empty region, wherein the grid map comprises a plurality of grids inside the empty region, and filling the empty region with a plurality of dummy fin cells by placing a dummy fin cell in each of the plurality of grids, wherein applying the grid map and filling the empty region is performed using a computer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.