Increasing parallel program performance for irregular memory access problems with virtual data partitioning and hierarchical collectives
US8869155B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 12, 2010 |
| Grant date | Oct 21, 2014 |
| Priority date | — |
| Expiry date | Aug 22, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/522
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for increasing performance of an operation on a distributed memory machine is provided. Asynchronous parallel steps in the operation are transformed into synchronous parallel steps. The synchronous parallel steps of the operation are rearranged to generate an altered operation that schedules memory accesses for increasing locality of reference. The altered operation that schedules memory accesses for increasing locality of reference is mapped onto the distributed memory machine. Then, the altered operation is executed on the distributed memory machine to simulate local memory accesses with virtual threads to check cache performance within each node of the distributed memory machine.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.