Array structure and fabricating method thereof
US8872184B2 · kind B2 · utility
3Cited by
6References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 25, 2010 |
| Grant date | Oct 28, 2014 |
| Priority date | — |
| Expiry date | Sep 6, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F1/1368
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
An array structure, which includes a TFT, a passivation layer, a pixel electrode, a first connecting layer and a first spacer is provided. The TFT includes a gate, a source and a drain. The passivation layer overlays the TFT. The pixel electrode is located on the passivation layer. The first connecting layer is located on the pixel electrode and electrically connected to the pixel electrode and the drain. The first spacer is located on the first connecting layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.