Externally configurable power-on-reset systems and methods for integrated circuits
US8872554B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 31, 2012 |
| Grant date | Oct 28, 2014 |
| Priority date | — |
| Expiry date | Jan 31, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/24
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Externally configurable power-on-reset systems and methods for integrated circuits are disclosed that utilize internal power-on-reset circuitry and reset control circuitry to provide operational configurations determined by external connections. In one configuration where no dedicated external reset signal is desired, the reset control circuitry relies upon the internal power-one-reset circuitry to generate the internal reset control signal. In another configuration where an external reset signal is utilized, the reset control circuitry relies upon the external reset signal, which overrides the internal power-on-reset circuitry, to generate the internal reset control signal. In further configurations, the reset control circuitry utilizes logic circuitry controlled through a digital interface to determine when the internal reset control signal can be de-asserted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.