Patent · US Active

ESD protection device with reduced clamping voltage

US8873210B2 · kind B2 · utility

1Cited by

1References

12Claims

0Family size

Assignees

IMEC VZW · BE
UNIVERSITEIT GENT · BE

Inventors

Ramses Pierco · Evergem, BE
Johan Bauwelinck · Temse, BE
Xin Yin · Jianghu, CN

Key dates

Filing date	Sep 10, 2012
Grant date	Oct 28, 2014
Priority date	—
Expiry date	Sep 10, 2032

Classification

Technology area (CPC H)Electricity
CPC primaryH02H9/046
WIPO fieldElectrical machinery, apparatus, energy
WIPO sectorElectrical engineering

Abstract

Disclosed is an ESD protection circuit comprising a plurality of bipolar transistors, namely a plurality of ESD current conducting transistors (Q1, Q2, Q4) in a main ESD current conducting path between a first and a second terminal (T1, T2), and further comprises at least one driving transistor (Q3) connected in parallel to at least one of the ESD current conducting transistors (Q1) and provided for conducting a driving current (Ib2) to one or more of the ESD current conducting transistors (Q3) on occurrence of an ESD event.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.