Hardware pixel processing pipeline and video processing instructions
US8873637B2 · kind B2 · utility
7Cited by
6References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 19, 2010 |
| Grant date | Oct 28, 2014 |
| Priority date | — |
| Expiry date | Dec 26, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/85
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A hardware pixel processing pipeline and a video processing instruction set accelerate image processing and/or video decompression. The pixel processing pipeline uses hardware components to more efficiently perform color space conversion and horizontal upscaling. Additionally, the pixel processing pipeline also reduces the size of its output data to conserve bandwidth. A specialized video processing instruction set allows further acceleration of video processing or video decoding by allowing receipt of a single instruction to cause multiple addition operation or interpolation of multiple pairs of pixels in parallel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.