Network interface for use in parallel computing systems
US8874797B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 17, 2012 |
| Grant date | Oct 28, 2014 |
| Priority date | — |
| Expiry date | Jan 17, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/9063
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A network device comprises a controller that manages data flow through a network interconnecting a plurality of processors. The processors of the processor plurality comprise a local memory divided into a private local memory and a public local memory, a local cache, and working registers. The network device further comprises a plurality of cache mirror registers coupled to the controller that receive data to be forwarded to the processor plurality. The controller is responsive to a request to receive data by transferring requested data directly to public memory without interrupting the processor, and by transferring requested data via at least one cache mirror register for a transfer to processor local cache, and to processor working registers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.