Vector processing circuit, command issuance control method, and processor system
US8874879B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 24, 2011 |
| Grant date | Oct 28, 2014 |
| Priority date | — |
| Expiry date | Nov 16, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3836
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A vector processing circuit includes a vector register file including a plurality of array elements, a command issuance control circuit, and a plurality of pipeline arithmetic units. Each pipeline arithmetic unit performs arithmetic processing of data stored in the array elements indicated as a source by one command in parts through a plurality of cycles and stores the result in the array elements indicated as a destination by the one command through a plurality of cycles. When data word length of a preceding command is longer than that of a subsequent command, the command issuance control circuit changes data sizes of the array elements in accordance with data word length of the command and determines whether there is register interference between the array element to be processed at a non-head cycle of the preceding command, and the array element to be processed at a head cycle of the subsequent command.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.