System and method for generating constrained random values associated with an electronic design
US8875069B1 · kind B1 · utility
2Cited by
1References
18Claims
0Family size
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Key dates
| Filing date | Jan 24, 2013 |
| Grant date | Oct 28, 2014 |
| Priority date | — |
| Expiry date | Jan 24, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2111/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to a computer-implemented method for electronic design verification. The method may include providing, using one or more processors, an electronic design having at least one floating point variable associated therewith. The method may further include converting the at least one floating point variable of the electronic design to a fixed point variable to generate a fixed point implementation of the electronic design. The method may also include processing, using a formal engine, the fixed point implementation of the electronic design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.