Fuse circuit for final test trimming of integrated circuit chip
US8878304B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 25, 2012 |
| Grant date | Nov 4, 2014 |
| Priority date | — |
| Expiry date | Aug 17, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/40
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention discloses a fuse circuit for final test trimming of an integrated circuit (IC) chip. The fuse circuit includes at least one electrical fuse, at least one control switch corresponding to the electrical fuse, and a resistant device. The electrical fuse is connected with the control switch in series between a predetermined pin and a grounding pin. The control switch receives a control signal to determine whether a predetermined current flows through the corresponding electrical fuse and breaks the electrical fuse. The resistant device is coupled between a bulk terminal and a source terminal to increase a resistance of a parasitic channel, such that an electrostatic discharge (ESD) protection is enhanced, and errors of final test trimming of an IC chip are avoided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.