Integrated circuit resistors with reduced parasitic capacitance

US8878334B1 · kind B1 · utility

Assignee

• Altera Corporation · US

Inventors

• Albert Ratnakumar · San Jose, US
• Peter Smeys · White Plains, US

Key dates

• Filing date: Mar 23, 2012
• Grant date: Nov 4, 2014
• Expiry date: Mar 23, 2032

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/811

Abstract

Integrated circuits that include resistors are provided. An integrated circuit resistor may include a conductive structure disposed over a semiconductor substrate. An oxide layer may be interposed between the conductive structure and a top surface of the semiconductor substrate. A shallow trench isolation structure may be formed in the substrate directly beneath the oxide layer. The shallow trench isolation structure may be formed in a given region in the substrate that is contained within a surrounding n-well and a deep n-well. The given region within which the shallow trench isolation structure is formed may exhibit native substrate dopant concentration levels; the given region is neither an n-well nor a p-well. The surrounding n-well and the deep n-well may be reversed biased to help fully deplete the given region so that parasitic capacitance levels associated with the resistor are minimized.