Method and apparatus for supplying power to a system on a chip (SOC)
US8878354B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | May 31, 2012 |
| Grant date | Nov 4, 2014 |
| Priority date | — |
| Expiry date | Dec 25, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package including i) a first semiconductor die and ii) a second semiconductor die vertically stacked on top of the first semiconductor die. The first semiconductor die includes a first electronic component and a second electronic component, in which the first electronic component operates in accordance with power associated with a first power domain, and the second electronic component operates in accordance with power associated with a second power domain. The second semiconductor die is configured to supply the power associated with the first power domain to the first electronic component of the first semiconductor die, and supply the power associated with the second power domain to the second electronic component of the first semiconductor die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.