Bond pad structure
US8878370B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 12, 2012 |
| Grant date | Nov 4, 2014 |
| Priority date | — |
| Expiry date | May 8, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/05552
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A bond pad structure for an integrated circuit chip package is disclosed. The bond pad structure includes a top metal layer, a patterned metal layer and an interconnection structure. The patterned metal layer is formed below the top metal layer and includes an annular metal layer and a plurality of metal blocks evenly arranged at a central area of the annular metal layer; the patterned metal layer is connected to the top metal layer through both the annular metal layer and the metal blocks. The interconnection structure is formed below the patterned metal layer and is connected to patterned metal layer only through the annular metal layer. By using the above structure, active or passive devices can be disposed under the bond pad structure and will not be damaged by package stress. An integrated circuit employing the above bond pad structure is also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.