Time-interleaved skew reduced pipelined analog to digital converter
US8878707B1 · kind B1 · utility
1Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 15, 2013 |
| Grant date | Nov 4, 2014 |
| Priority date | — |
| Expiry date | Aug 15, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/164
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system includes a first storage element to store an input signal for a first sampling lane for a SHA-less stage. A first switch is connected with the first storage element, the first switch to control when the first storage element stores the input signal for sampling on the first sampling lane. A second switch is connected in series with the first switch, the second switch to control an instance for sampling the input signal stored on the first storage element for the first sampling lane.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.