Equalization adaptation using timing detector
US8879615B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 14, 2013 |
| Grant date | Nov 4, 2014 |
| Priority date | — |
| Expiry date | Mar 14, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2025/03356
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An equalization adaptation circuit comprises an equalizer, a transition determination circuit, a phase error circuit, a sequence recovery circuit, a phase error accumulator circuit, a transition accumulator circuit, and a controller circuit. The equalizer has adjustable parameters. The transition determination circuit determines observed transitions in an equalized signal output from the equalizer. A phase error circuit determines phase errors of the observed transitions. A sequence recovery circuit generates recovered digital data sequences. A phase error accumulator circuit accumulates the phase errors in respective association with pre-defined patterns matching the recovered digital data sequences containing observed transitions corresponding to the phase errors. A transition accumulator circuit accumulates a number of the observed transitions. A controller circuit controls the adjustable parameters of the equalizer based upon the accumulated phase errors and number of observed transitions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.