Multi-channel bit packing engine
US8879858B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 25, 2014 |
| Grant date | Nov 4, 2014 |
| Priority date | — |
| Expiry date | Feb 25, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N23/843
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A system and method are provided for packing compressed image data into a format suitable for encoding. The system includes a plurality of sub-band state registers, which store compressed image data from a corresponding sub-band. A bit packer receives a stream of bits of compressed image data, and concatenates the input bits with bits stored in one of the sub-band state registers. If a length of the concatenated bits is less than a width of an output data bus, the bit packer stores the concatenated bits in the sub-band state register. If the length of the concatenated bits is greater than or equal to the width of the output data bus, the bit packer outputs the concatenated bits via the output data bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.