Debugging a memory subsystem
US8880779B2 · kind B2 · utility
12Cited by
4References
31Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 5, 2011 |
| Grant date | Nov 4, 2014 |
| Priority date | — |
| Expiry date | Oct 28, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/263
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one implementation, a memory subsystem includes non-volatile memory, a memory controller that is communicatively connected to the non-volatile memory over a first bus, a host interface through which the memory controller communicates with a host controller over a second bus, and a joint test action group (JTAG) interface that provides the host controller with access to state information associated with the memory controller. The memory subsystem can be configured to be coupled to a board-level memory device that includes the host controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.