Data processing device and data processing arrangement for accelerating buffer synchronization

US8880811B2 · kind B2 · utility

Assignee

• Intel Mobile Communications GmbH · DE

Inventors

• Mirko Sauermann · Neubiberg, DE
• Alexander Schackow · Hersbruck, DE
• Cyprian Grassmann · Deisenhofen, DE
• Ulrich Hachmann · Pyrbaum, DE
• Ronalf Kramer · Hersbruck, DE
• Dominik Langen · Unterschleißheim, DE
• Wolfgang Raab · Hersbruck, DE

Key dates

• Filing date: Jun 27, 2011
• Grant date: Nov 4, 2014
• Expiry date: Oct 28, 2032

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F15/167
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A data processing device is described with a memory and a first and a second data processing component. The first data processing component comprises a control memory comprising, for each memory region of a plurality of memory regions of the memory, an indication whether a data access to the memory region may be carried out by the first data processing component and a data access circuit configured to carry out a data access to a memory region of the plurality of memory regions if a data access to the memory region may be carried out by the first data processing component; and a setting circuit configured to set the indication for a memory region to indicate that a data access to the memory region may not be carried out by the first data processing component in response to the completion of a data access of the first data processing component to the memory region.