Stored program writing stall information when a processor stalls waiting for another processor
US8881114B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 15, 2006 |
| Grant date | Nov 4, 2014 |
| Priority date | — |
| Expiry date | Sep 4, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3648
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system of inserting marker values used to correlate trace data as between processor cores. At least some of the illustrative embodiments are integrated circuit devices comprising a first processor core, a first data collection portion coupled to the first processor core and configured to gather data comprising addresses of instructions executed by the first processor core, a second processor core communicatively coupled to the first processor core, and a second data collection portion coupled to the first processor core and configured to gather data comprising addresses of instructions executed by the second processor core. The integrated circuit device is configured to insert marker values into the data of the first and second processor cores which allow correlation of the data such that contemporaneously executed instruction are identifiable.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.