Method of fabricating and semiconductor memory device using the same
US8883622B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 7, 2012 |
| Grant date | Nov 11, 2014 |
| Priority date | — |
| Expiry date | Mar 7, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a semiconductor memory device includes preparing a semiconductor substrate which is divided into a cell array region and a core and peripheral region adjacent to the cell array region. Signal lines may be formed in a lower layer in a cell region. An insulation layer may be formed on the lower layer. Signal lines connected to cell region signal lines may be formed on an insulation layer of the peripheral region. A capping layer may be formed on the insulation layer and the core and peripheral signal lines. The capping layer may be etched to expose the lower layer of the cell array region and an etch stop may be formed on the lower layer and the core and peripheral region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.