Semiconductor structure with means for testing metal-insulator-metal capacitors
US8884288B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2013 |
| Grant date | Nov 11, 2014 |
| Priority date | — |
| Expiry date | Sep 30, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/34
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides a semiconductor structure for testing MIM capacitors. The semiconductor structure comprises: a first metal layer comprising at least a first circuit area and a second circuit area; a second metal layer located below the first metal layer with a first dielectric layer lying therebetween and connected with the second circuit area; a top plate located within the first dielectric layer closer to the first metal layer and connected with the first circuit area; a bottom plate located within the first dielectric layer closer to the second metal layer and separated from the top plate with an insulation layer therebetween and connected with the second circuit area. The second metal layer is connected with the substrate through a first electric pathway so as to form a second electric pathway from the top plate to the substrate when an electric leakage region exists in the insulation layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.