CMOS device and fabrication method
US8884374B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 18, 2013 |
| Grant date | Nov 11, 2014 |
| Priority date | — |
| Expiry date | Jan 18, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/85
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Various embodiments provide complementary metal-oxide-semiconductor (CMOS) devices and their fabrication methods. A semiconductor substrate is provided to include a first region to form a PMOS transistor and a second region to form an NMOS transistor. One of the first and second regions can include a metal gate structure having a metal top layer. The other of the first and second regions can include an interfacial oxide layer formed on a high-k dielectric layer. A surface of the metal top layer can be oxidized to form a metal oxide top layer covering the metal top layer. The metal oxide top layer and the interfacial oxide layer can be removed by wet etching. A metal gate can be formed on the high-k dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.