Process of ultra thick trench etch with multi-slope profile
US8884441B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 18, 2013 |
| Grant date | Nov 11, 2014 |
| Priority date | — |
| Expiry date | Feb 18, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to an integrated chip (IC) having an ultra-thick metal layer formed in a metal layer trench having a rounded shape that reduces stress between an inter-level dielectric (ILD) layer and an adjacent metal layer, and a related method of formation. In some embodiments, the IC has an inter-level dielectric layer disposed above a semiconductor substrate. The ILD layer has a cavity with a sidewall having a plurality of sections, wherein respective sections have different slopes that cause the cavity to have a rounded shape. A metal layer is disposed within the cavity. The rounded shape of the cavity reduces stress between the ILD layer and the metal layer to prevent cracks from forming along an interface between the ILD layer and the metal layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.