High-speed analog-to-digital conversion system with flash assisted parallel SAR architecture
US8884801B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 21, 2013 |
| Grant date | Nov 11, 2014 |
| Priority date | — |
| Expiry date | Nov 21, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/466
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention is directed to signal processing systems and methods thereof. In various embodiments, the present invention provides an analog-to-digital conversion (ADC) system that includes a flash ADC portion and a time-interleaved parallel SAR portion. For an n-bit ADC process, the flash ADC portion converts k MSBs of the n bits during a single cycle, and the SAR portion converts n−k LSBs in m number of cycles. The SAR portion includes a number of SAR channels that perform A/D conversion in parallel, and the k MSB from the course flash converter is verified for errors by the SAR portion and allows a net saving of the power consumption by reducing the number of fine resolution SARs. There are other embodiments as well.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.