Method and apparatus for ESD circuits
US8885305B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 25, 2012 |
| Grant date | Nov 11, 2014 |
| Priority date | — |
| Expiry date | Oct 20, 2032 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/4913
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A high performance ESD protection circuit is provided. Embodiments include a circuit having an RC clamp circuit including a first NMOS transistor having a first source, drain, and gate, a current mirror circuit including first and second PMOS transistors having a second and third source, drain, and gate, respectively, and an SCR circuit including a first P+ contact. The first source is coupled to a ground rail, the first drain is coupled to the second drain, second gate, and third gate, the second and third sources are coupled to a power rail, and the third drain is coupled to the first P+ contact, wherein during an ESD event the first NMOS and PMOS transistors turn on to discharge a first current to the ground rail, and the current mirror provides a second current to the first P+ contact for turning on the SCR.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.