Memory array voltage source controller for retention and write assist
US8885393B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2012 |
| Grant date | Nov 11, 2014 |
| Priority date | — |
| Expiry date | Dec 18, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/417
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A voltage source controller for a memory array includes an input coupled to a voltage source, an output coupled to one or more memory cells of a memory array, where the output is configured to provide a cell source voltage to the memory cells. The controller also includes a switch circuit configured to: receive a retention enable signal, a write assist enable signal, and a standard mode enable signal; and based on the retention enable signal, write assist enable signal, and standard mode enable signal, selectively set the cell source voltage for one or more of the memory cells to one of: a retention voltage, a write assist voltage, or a standard mode voltage, where the retention voltage and the write assist voltage are less than the standard mode voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.