Radio architecture for an ultra low power receiver
US8885773B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 22, 2011 |
| Grant date | Nov 11, 2014 |
| Priority date | — |
| Expiry date | May 19, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2027/0055
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An ultra low power radio receiver architecture based on phase locked loop is provided. Embodiments of an ultra low power radio receiver architecture based on phase locked loop can detect a complex modulated MSK signal with only a single path receiver chain. According to an embodiment of the present invention, the overall power consumption of the radio receiver in the present invention can be reduced by almost fifty percent compared to that of the conventional complex path radio receiver architecture. The radio receiver architecture of the invention is suitable for the ultra low power radio application such as wireless sensor networks (WSN).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.