Reducing settling time in phase-locked loops
US8885788B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 15, 2013 |
| Grant date | Nov 11, 2014 |
| Priority date | — |
| Expiry date | May 15, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/093
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit may include a phase detector configured to generate a phase error signal based on a feedback signal and an oscillator configured to generate an output signal. The feedback signal may be based on the output signal. The circuit may also include a determination unit configured to measure a phase of the feedback signal based on the phase error signal when an output of the phase detector and an input of the oscillator are communicatively decoupled. The circuit may also include an adjustment unit configured to subtract the measured phase of the feedback signal from an intermediate signal upon which the output signal is based when the output of the phase detector and the input of the oscillator are communicatively coupled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.