Encoder and encoding method providing incremental redundancy
US8887030B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 18, 2011 |
| Grant date | Nov 11, 2014 |
| Priority date | — |
| Expiry date | Nov 23, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2001/0098
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The present invention relates to an encoder for error correction code encoding input data words (D) into codewords (Z1, Z2), comprising: an encoder input (1451) for receiving input data words (D) each comprising a first number Kldpc of information symbols, an encoding means (1452) for encoding an input data word (D) into a codeword (Z1, Z2, Z3, Z4) such that a codeword comprises a basic codeword portion (B) including a data portion (D) and a basic parity portion (Pb) of a second number Nldpc−Kldpc of basic parity symbols, and an auxiliary codeword portion (A) including an auxiliary parity portion (Pa) of a third number MIR of auxiliary parity symbols, wherein said encoding means (14) is adapted i) for generating said basic codeword portion (B) from an input data word (D) according to a first code, wherein a basic parity symbol is generated by accumulating an information symbol at a parity symbol address determined according to a first address generation rule, and ii) for generating said auxiliary codeword portion (A) from an input data word (D) according to a second code, wherein an auxiliary parity symbol is generated by accumulating an information symbol m at a parity symbol addr…
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