Recess gate transistor
US8889539B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 11, 2008 |
| Grant date | Nov 18, 2014 |
| Priority date | — |
| Expiry date | Jul 23, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/027
Abstract
A method of forming a semiconductor device is provided, comprising forming a plurality of hard masks on a substrate by patterning an insulating layer; forming a plurality of trenches in the substrate, each trench having trench walls disposed between two adjacent masks and extending vertically from a bottom portion to an upper portion; forming an insulating layer on the hard masks and the trench walls; forming a conductive layer on the insulating layer; etching the conductive layer to form conductive layer patterns to fill the bottom portions of the trenches; depositing a buffer layer on the conductive layer patterns and the trench walls; and filling the upper portions of the trenches with a capping layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.