Patent · US Active

Clock gating latch, method of operation thereof and integrated circuit employing the same

US8890573B2 · kind B2 · utility

18Cited by

6References

20Claims

0Family size

Assignee

NVIDIA Corporation · US

Inventors

Ilyas Elkin · Sunnyvale, US
Ge Yang · Beijing, CN
Jonah M. Alben · San Jose, US

Key dates

Filing date	Sep 7, 2012
Grant date	Nov 18, 2014
Priority date	—
Expiry date	Sep 7, 2032

Classification

Technology area (CPC H)Electricity
CPC primaryH03K19/0016
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A clock gating latch, a method of gating a clock signal and an integrating circuit incorporating the clock gating latch or the method. In one embodiment, the clock gating latch includes: (1) a propagation circuit having a single, first switch configured to be driven by an input clock signal, (2) a keeper circuit coupled to the propagation circuit and having a single, first switch configured to be driven by the input clock signal and (3) an AND gate coupled to the propagation circuit and the keeper circuit and having an internal node coupled to a second switch in the propagation circuit and a second switch in the keeper circuit.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.